CPU Pipelining
Step through a 5-stage MIPS pipeline with hazard detection and forwarding
Pipeline State — Cycle 0
IF
ID
EX
MEM
WB
1/1
Load a program to see the timing diagram
Pipeline Statistics
Instructions:3
Total Cycles:0
Stall Cycles:0
CPI:0.00
Step through a 5-stage MIPS pipeline with hazard detection and forwarding